129 lines
3.1 KiB
C++
129 lines
3.1 KiB
C++
// Copyright 2014 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <algorithm>
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#include <cstring>
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#include <memory>
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#include "core/arm/dyncom/arm_dyncom.h"
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#include "core/arm/dyncom/arm_dyncom_interpreter.h"
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#include "core/arm/dyncom/arm_dyncom_trans.h"
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#include "core/arm/skyeye_common/armstate.h"
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#include "core/core.h"
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#include "core/core_timing.h"
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namespace Core {
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ARM_DynCom::ARM_DynCom(Core::System& system_, Memory::MemorySystem& memory,
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PrivilegeMode initial_mode, u32 id,
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std::shared_ptr<Core::Timing::Timer> timer)
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: ARM_Interface(id, timer), system(system_) {
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state = std::make_unique<ARMul_State>(system, memory, initial_mode);
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}
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ARM_DynCom::~ARM_DynCom() {}
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void ARM_DynCom::Run() {
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ExecuteInstructions(std::max<s64>(timer->GetDowncount(), 0));
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}
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void ARM_DynCom::Step() {
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ExecuteInstructions(1);
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}
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void ARM_DynCom::ClearInstructionCache() {
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state->instruction_cache.clear();
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trans_cache_buf_top = 0;
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}
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void ARM_DynCom::InvalidateCacheRange(u32, std::size_t) {
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ClearInstructionCache();
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}
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void ARM_DynCom::SetPageTable(const std::shared_ptr<Memory::PageTable>& page_table) {
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ClearInstructionCache();
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}
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std::shared_ptr<Memory::PageTable> ARM_DynCom::GetPageTable() const {
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return nullptr;
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}
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void ARM_DynCom::SetPC(u32 pc) {
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state->Reg[15] = pc;
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}
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u32 ARM_DynCom::GetPC() const {
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return state->Reg[15];
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}
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u32 ARM_DynCom::GetReg(int index) const {
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return state->Reg[index];
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}
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void ARM_DynCom::SetReg(int index, u32 value) {
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state->Reg[index] = value;
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}
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u32 ARM_DynCom::GetVFPReg(int index) const {
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return state->ExtReg[index];
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}
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void ARM_DynCom::SetVFPReg(int index, u32 value) {
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state->ExtReg[index] = value;
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}
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u32 ARM_DynCom::GetVFPSystemReg(VFPSystemRegister reg) const {
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return state->VFP[reg];
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}
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void ARM_DynCom::SetVFPSystemReg(VFPSystemRegister reg, u32 value) {
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state->VFP[reg] = value;
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}
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u32 ARM_DynCom::GetCPSR() const {
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return state->Cpsr;
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}
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void ARM_DynCom::SetCPSR(u32 cpsr) {
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state->Cpsr = cpsr;
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}
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u32 ARM_DynCom::GetCP15Register(CP15Register reg) const {
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return state->CP15[reg];
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}
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void ARM_DynCom::SetCP15Register(CP15Register reg, u32 value) {
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state->CP15[reg] = value;
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}
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void ARM_DynCom::ExecuteInstructions(u64 num_instructions) {
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state->NumInstrsToExecute = num_instructions;
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const u32 ticks_executed = InterpreterMainLoop(state.get());
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if (timer) {
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timer->AddTicks(ticks_executed);
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}
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state->ServeBreak();
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}
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void ARM_DynCom::SaveContext(ThreadContext& ctx) {
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ctx.cpu_registers = state->Reg;
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ctx.cpsr = state->Cpsr;
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ctx.fpu_registers = state->ExtReg;
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ctx.fpscr = state->VFP[VFP_FPSCR];
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ctx.fpexc = state->VFP[VFP_FPEXC];
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}
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void ARM_DynCom::LoadContext(const ThreadContext& ctx) {
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state->Reg = ctx.cpu_registers;
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state->Cpsr = ctx.cpsr;
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state->ExtReg = ctx.fpu_registers;
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state->VFP[VFP_FPSCR] = ctx.fpscr;
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state->VFP[VFP_FPEXC] = ctx.fpexc;
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}
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void ARM_DynCom::PrepareReschedule() {
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state->NumInstrsToExecute = 0;
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}
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} // namespace Core
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